Linux 6.12 boots on ESP32-S31: a RISC-V port full of guesswork
An independent developer got Linux 6.12 running on Espressif's ESP32-S31, a RISC-V MCU with a non-standard supervisor mode and no official TRM. The port leans on CLIC patches, XIP in flash, and a lot of probing.

Linux on a microcontroller is usually a party trick, but this one is different. GrieferPig has ported Linux 6.12 to the ESP32-S31, Espressif's latest RISC-V part, and the boot log shows a real userspace with a shell, CoreMark, and 15 MB of RAM visible to the kernel. The catch: the S31's architecture is RV32IMAFBCNSUX, and its supervisor mode is anything but standard.
The port targets the ESP32-S31-WROOM-3 module and boots a mainline kernel with OpenSBI. Because the chip's TRM wasn't available at the time, the developer made educated guesses based on the P4's TRM and CSR probing. That shows in the quirks section: the S31 uses CLIC and CLINT instead of the PLIC Linux expects, and the standard RISC-V interrupt CSRs are unusable because mtvec.MODE is hardwired to CLIC mode. A custom CLIC driver, borrowed from a litex-hub PR, gets interrupts working.
Supervisor mode is even weirder. The S31 implements something called SCLIC, which isn't standardized anywhere. The developer found that mcliccfg.NMBITS is writable despite ESP-IDF docs saying otherwise, and setting it to 0b01 unlocks S-mode interrupt configuration. That's the kind of discovery that only happens when you're poking at hardware without a datasheet.
Memory is tight: the chip has 16 MB of PSRAM, and to save it, OpenSBI runs XIP from flash and internal SRAM. That's why the firmware size in the banner is a weird 3.9 GB—flash and SRAM mappings aren't contiguous. Mainline Linux dropped RISC-V XIP support, so the port uses 6.12, the last version with it.
The driver status table is mostly yellow. UART, GPIO, Ethernet, SDMMC, and cache drivers are untested; USB, timers, clock tree, and security accelerators are WIP; I2C, I2S, SPI, RMT, and the LP subsystem are not implemented. Dual-hart SMP is not planned because FreeRTOS owns the second core. The boot log shows a single hart with rv32imafc and an MMU, running a shell with 15 MB free.
CoreMark scores 1058 iterations per second with GCC 15.2 at -O2. That's not a benchmark to write home about, but it's a full Linux userspace on a chip that Espressif never intended to run it.
According to all laws of esp-idf, mcliccfg.NMBITS is not writable. IT IS WRITABLE!
| Feature | Status |
|---|---|
| UART0 console | Untested |
| GPIO | Untested |
| GMAC Ethernet | Untested |
| SDMMC | Untested |
| USB | WIP |
| Timers | WIP |
| Clock tree | WIP |
| Security accelerators | WIP |
| I2C | Not Implemented |
| I2S | Not Implemented |
| SPI | Not Implemented |
| RMT | Not Implemented |
| LP subsystem & IPC | Not Implemented |
| PMP/APM | Not Implemented (properly) |
| Dual hart SMP | Not Planned |
Source: GitHub