NVIDIA’s Vera Whitepaper: Great Silicon, Shaky Story

NVIDIA’s 45-page Vera whitepaper is a tale of two documents. The hardware described inside is genuinely impressive—an 88-core monolithic die built around the company’s own Olympus cores, each a 10-wide Arm v9.2 design with value prediction, a graph prefetcher, 2 MB of private L2, and a shared 164 MB last-level cache. Eight LPDDR5X interfaces promise 1.2 TB/s of memory bandwidth. Early independent testing suggests Vera is the fastest Arm server CPU we’ve seen in public benchmarks.

But the whitepaper spends too much time trying to frame x86 as a strawman. Traditional SMT is caricatured as “time-slicing,” a configurable NUMA topology is presented as an unavoidable maze, and undefined performance-counter ratios are promoted as causal proof. The frustrating part is that Vera doesn’t need this help—the hardware stands on its own. Let’s pull the story apart.

Olympus: A Genuinely Formidable Core

The Olympus core is wide and aggressive. It decodes ten instructions per cycle, handles two taken branches per cycle, and includes a neural branch predictor, value prediction, memory renaming, a large instruction window, six 128-bit SVE pipes, four load pipes, two store pipes, and a 96 KB L1 data cache. The 2 MB private L2 is accessible in roughly 10 cycles. Eighty-eight of these cores sit behind a 3.4 TB/s coherency fabric and a distributed 164 MB system-level cache.

Value prediction is one of the more unique additions. While Apple has been discovered to use it, and AMD experimented with it in Zen 1/2, Olympus appears to implement it more broadly—closer to Apple’s approach. The graph prefetcher, however, is not new: Intel’s Data-Dependent Prefetcher and Array of Pointers prefetcher implement the same producer-consumer idea, albeit more constrained. And “neural branch predictors” date back to AMD’s Piledriver in 2012, later refined with TAGE.

The memory subsystem is equally beefy: eight SOCAMM2 LPDDR5X modules provide up to 1.5 TB capacity and 1.2 TB/s bandwidth, with NVIDIA claiming only ~50 W power draw. That’s a tradeoff—conventional EPYC/Xeon platforms offer higher-capacity, replaceable DIMMs but pay in board area and power.

The SMT Strawman

The whitepaper’s Figure 5 contrasts “Traditional SMT (x86)” with NVIDIA’s “Spatial Multithreading,” depicting x86 as alternating threads through the pipeline while NVIDIA partitions resources. This is misleading. Real SMT implementations share stages by selecting a thread per cycle or behaving thread-agnostically, allowing both threads to use execution units in the same cycle. Static partitioning, as NVIDIA implies, can leave throughput on the table when one thread stalls.

NVIDIA emphasizes “determinism, isolation, and quality of service” for its approach—conspicuously not performance. QoS may be a valid priority for their target market, but the diagram makes it look like a performance win when it’s really a design choice.

Benchmarks: Strong, But Caveated

Phoronix’s early testing showed Vera’s geomean 10% above a 5 GHz EPYC 9575F, 1.55x a Xeon 6980P, and 1.63x Grace—making it the most performant Arm server CPU in public testing. But NVIDIA chose the permitted workload scope, disallowed frequency/power monitoring, and the system was pre-production with a one-day test window. Broader coverage will have to wait for production hardware.

The hardware is real. The marketing around it is not. Engineers should read the whitepaper for the architecture, not the narrative.