AMD GFX1250: LLVM Commits Reveal MI455X Architecture Details

AMD's next-gen datacenter accelerator, the MI455X (codenamed GFX1250), is getting preliminary support in LLVM, and the commits paint a clear picture of a compute monster stripped of all graphics vestiges. The chip will power the Helios rack and is set to be unveiled at AMD's Advancing AI event.

Architecture Deep Dive

GFX1250 is Wave32-only — a departure from CDNA's Wave64-only design and RDNA's dual-mode capability. This means existing CDNA kernels will need re-evaluation. Each SIMD can now address up to 1024 VGPRs, a massive jump from CDNA4's split 256+256 allocation and RDNA's 256-register cap. That's a boon for ML workloads with high register pressure.

The most significant change is the unification of LDS and vector L0 cache into a single 448KB WGP Cache (WGP$), matching what Nvidia and Intel have done for years. AMD was the last holdout with split structures. The maximum addressable LDS per wavefront doubles to 320kB, and the actual LDS can be larger thanks to the unified pool.

Dynamic VGPR allocation, a headline feature of RDNA4, is notably absent — the instruction is a no-op. This is surprising given ML workloads' register hunger. Packed FP32 operations (two FP32 ops per lane) carry over from CDNA2, effectively doubling vector width vs. RDNA.

Compute-Only, No Graphics

GFX1250 strips out nearly all graphics hardware: no rasterizer, no texture instructions, no BVH (raytracing), no vertex interpolation, and — unlike prior CDNA — no typed or untyped buffer instructions. This is a pure compute accelerator, saving die space for what matters.

Tensor Operations: Best of Both Worlds

The WMMA tensor units combine RDNA4's simpler programming model with CDNA4's broader format support. Matrix dimensions stay M=N=16, with K varying by type: K=4 for FP64/FP32, K=32 for FP16, K=64 for INT8, K=128 for FP8. INT4 stays at K=32 (RDNA4 level). GFX1250 supports all data types from both CDNA4 and RDNA4 except FP64, which is reserved for the HPC-oriented GFX1251 (MI430X). OCP MX-style scaling is included.

New LDS submatrix transpose instructions complement RDNA4's offerings, and sparse WMMA keeps K the same (doing less work per instruction than dense).

Overall, GFX1250 looks like a carefully tuned ML workhorse. The unified cache and massive register file should help close the gap with Nvidia's Blackwell, though we'll need real benchmarks to know for sure.